The invention relates to a memory cell array and a method for manufacturing it.
At present, what is referred to as a single-transistor memory cell, comprising a transistor and a capacitor, is used almost exclusively as the memory cell of a DRAM cell array, i.e. a memory cell array with dynamic random access. The information of the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor in such a way that when the transistor is switched on via a word line, the charge of the capacitor can be read out via a bit line.
The general aim is to produce a DRAM cell array which has a high packing density.
EP 0852396 A2 describes a DRAM cell array which comprises single-transistor memory cells. The transistor of a memory cell is embodied as a vertical transistor and is arranged on an edge of a depression in a substrate. The depression is arranged in a rectangular region which is surrounded by an insulating structure and adjoins the insulating structure with a first edge. An upper source/drain region and a lower source/drain region of the transistor, which are arranged in the substrate, adjoin a second edge of the depression lying opposite the first edge. A memory node of a capacitor of the memory cell which adjoins the lower source/drain region is arranged in a lower part of the depression. A bit line is arranged on the upper source/drain region. An insulated word line, which has downwardly directed bulges which extend into the depressions of the memory cells and act as gate electrodes of the transistors of the memory cells, is arranged over the bit line.
U.S. Pat. No. 4,630,088 describes a DRAM cell array which comprises single-transistor memory cells. The transistor of a memory cell is embodied as a vertical transistor. An upper and a lower source/drain region are parts of a parallelepiped-shaped projection of a substrate and are surrounded in annular fashion by a gate electrode. The upper source/drain region serves simultaneously as a capacitor electrode of a capacitor of the memory cell. A bit line is arranged over the capacitor electrode and serves simultaneously as a further capacitor electrode of the storage capacitor.
The invention is based on the problem of disclosing a further memory cell array in which a memory cell comprises a transistor and a capacitor. In addition, the intention is to disclose a manufacturing method for such a memory cell array.
The problem is solved by means of a memory cell array in which a memory cell comprises a transistor and a capacitor and has the following features:
First trenches which are parallel to one another and second trenches which run transversely with respect to the first trenches are provided in a substrate. An upper source/drain region of the transistor is arranged in the substrate and adjoins two of the first trenches and two of the second trenches. A lower source/drain region of the transistor is arranged in the substrate, under the upper source/drain region. The transistor is therefore embodied as a vertical transistor. Conductive structures, which each adjoin one of the upper source/drain regions at a first edge of the associated first trench and are insulated from a second edge and from the bottom of the first trench by an insulating structure arranged in the first trench, are arranged in the first trenches between the second trenches. A word line runs parallel to the first trenches and has bulges which extend into the second trenches. Parts of the word line which are arranged between the second trenches are arranged over an insulating layer. The insulating layer is arranged over the upper source/drain region. A further insulating layer is arranged on the word line. Insulating spacers adjoin the word line laterally. The capacitor is connected to the upper source/drain region via a contact which is arranged on the conductive structure and between word lines.
The problem is also solved by means of a method for manufacturing a memory cell array in which first trenches which run essentially parallel to one another are produced in a substrate. The first trenches are filled with insulating material. The insulating material is partially replaced with conductive material in such a way that the conductive material adjoins first edges, and the insulating material adjoins second edges and bottoms, of the first trenches. An insulating layer which covers the conductive material is produced. Second trenches which run essentially parallel to one another and transversely with respect to the first trenches are produced in the substrate in such a way that conductive structures which are separated from one another are produced from the conductive material and insulating structures which are separated from one another are produced from the insulating material. Upper source/drain regions of vertical transistors, and below them lower source/drain regions of the transistors, are produced in the substrate in such a way that the upper source/drain regions each adjoin a surface of the substrate, two of the first trenches and two of the second trenches. Word lines are generated parallel to the first trenches in such a way that they have bulges which extend into the second trenches and in each case partially overlap two of the first trenches. The word lines are insulated by a further insulating layer produced over them, and by spacers. The insulating layer is etched selectively with respect to the further insulating layer and with respect to the spacers in such a way that the conductive structures are exposed. Capacitors are generated which are connected to the conductive structures via contacts.
The conductive structure adjoins the upper source/drain region laterally and is separated from the rest of the substrate by the insulating structure. The conductive structure makes it possible to make contact with the upper source/drain region from above although the word line is arranged over the upper source/drain region. Because the conductive structure and the upper source/drain region overlap over a large area, a contact resistance between the capacitor and the transistor is particularly small.
The memory cell array can be manufactured with a high packing density because the manufacturing method has a large number of self-aligned process steps, i.e. process steps without masks which have to be aligned or process steps with large alignment tolerances. For example, the upper source/drain region and the capacitor can be placed in contact without precise alignment. Because the word line does not cover the conductive structure, it is possible to etch selectively with respect to the further insulating layer and with respect to the insulating spacers so that the contacts themselves are then produced between word lines which are adjacent to one another if the alignment of the contacts with respect to the upper source/drain regions is imprecise. The upper source/drain region can be produced self-aligned with respect to the first trenches and to the second trenches. To do this, it is possible, for example, to implant the substrate after the first and second trenches have been produced. Alternatively, before the first trenches and/or the second trenches are produced, a doped layer is produced in the substrate by implantation, and said doped layer is patterned by the first trenches and the second trenches with the result that the upper source/drain regions are produced from the doped region. The lower source/drain regions can also be produced self-aligned under the upper source/drain regions. For example, the lower source/drain region is part of a buried doped layer of the substrate. The alignment tolerance of the word line is large because all that is necessary is to fulfill the condition that the bulges extend into the second trenches where they can act as gate electrodes of the transistors, and that the upper source/drain region of the adjacent memory cell is not exposed during the selective etching in order to produce the contact of a memory cell.
In order to fulfill the condition just mentioned, a width of the word line is preferably greater than a width of the upper source/drain region. As a result, the alignment tolerance for producing the word line is increased and consequently the process reliablility is improved. In this case, the word line partially overlaps the two first trenches.
The space required for each memory cell of the memory cell array can be 4F2, F being the minimum structural size which can be manufactured in the technology used. To do this, the first and second trenches have a width of F. Distances between adjacent first trenches or adjacent second trenches are then also F.
In order to produce a particularly wide word line, it is possible to initially deposit conductive material over the entire area. A strip-shaped word line mask is then produced, the strips of which have a width of F and are at a distance of F from one another. The strips of the word line mask are subsequently widened by depositing material and etching it back so that spacers are produced on side faces of the word line mask. The conductive material can then be structured to form the word lines using the widened word line mask.
The memory cell array can be manufactured in such a way that the word line has a high electrical conductivity because parts of the word line are not buried in the substrate and can consequently be manufactured from metal. In order to produce such a word line, doped polysilicon is firstly deposited and then a metal or a metal silicide. Both materials are then structured with the word line mask. The lower source/drain region can be connected to a bit line which runs transversely with respect to the word line. The bit line is arranged in a lower part of the second trench and adjoins the lower source/drain region at a first edge of the second trench.
In order to avoid floating body effects, the lower source/drain region preferably adjoins only one of the two second trenches and is at a distance from the other of the two second trenches. The lower source/drain region can, for example, be produced by diffusing dopant out of the bit line.
The lower source/drain region can alternatively be produced from the buried doped layer of the substrate which is structured by means of the second trenches.
In order to avoid leakage currents, lower source/drain regions of transistors which are adjacent to one another along the second trench are preferably separated from one another by means of the first trenches.
Alternatively, the first trenches are only of such a depth that they separate the upper source/drain regions of these transistors from one another but not the lower source/drain regions of these transistors.
In order to increase the electrical conductivity of the bit line, the bit line can contain metal. A lower part of the bit line is preferably composed of metal and an upper part of the bit line, which adjoins the lower source/drain region, is preferably composed of polysilicon. A diffusion barrier separates the two parts from one another.
The bit line can be embodied as part of a capacitor electrode. In this case, it runs above the substrate. Lower source/drain regions of transistors which are adjacent to one another along one of the first trenches can be connected to one another in this case. Preferably, the buried doped layer is provided which is not divided by the first trenches and the second trenches.
The conductive structures can, for example, be produced in that a protective layer is initially produced on the substrate before the first trenches are produced. The protective layer is composed, for example, of silicon nitride or of some other material which is preferably insulating. The insulating material is replaced with the conductive material in such a way that, using a strip-shaped mask whose strips run parallel to the first trenches and in each case partially overlap one of the first trenches, the insulating material is etched selectively with respect to the protective layer to a depth which lies above the bottoms of the first trenches and the conductive material is then deposited and etched back until the protective layer is exposed.
The memory cell array can be a DRAM cell array. In order to increase the capacitances of the capacitors, the capacitors have a capacitor dielectric which preferably has a dielectric constant which is more than 20. The capacitor dielectric is composed, for example, of a ferroelectric with a Curie temperature of less an xe2x88x9250xc2x0 C., for example barium strontium titanate, or of Ta2O5.
The memory cell array can be a FRAM memory cell array. In this case, the capacitors have a capacitor dielectric which has a ferroelectric with a Curie temperature preferably of more than 200xc2x0 C.
An exemplary embodiment of the invention is explained below in more detail with reference to the figures, of which: